Blackfin® Embedded Symmetric Multiprocessor ADSP-BF561 Rev. B is a dual core 600 MHz high performance processor from Analog Devices, Inc. It features 328K bytes of on-chip memory and a RISC-like register and instruction model for ease of programming and compiler-friendly support. Additionally, the processor provides advanced debug, trace, and performance monitoring capabilities, and supports 0.8 V to 1.35 V core VDD as well as 2.5 V and 3.3 V compliant I/O.
The ADSP-BF561 is a dual‑core Blackfin processor featuring 600 MHz symmetric cores, 328 KB of on‑chip memory, and a rich set of arithmetic units including MACs, ALUs, video ALUs and a 40‑bit shifter. It supports low‑power operation with a core voltage range of 0.8 V‑1.35 V, on‑chip voltage regulation, and 2.5 V/3.3 V I/O levels. Various package options are offered, such as 256‑ball CSP‑BGA and 297‑ball PBGA.
The device includes extensive peripheral blocks: dual 12‑channel DMA controllers, UART with IrDA, dual SPORT ports, SPI, parallel peripheral interfaces, 12 programmable 32‑bit timers with PWM, dual watchdog timers, and 48 GPIO flags. Memory architecture spans L1 instruction/data caches, L2 SRAM, and external memory interfaces supporting SDRAM, flash, and SRAM. The handbook also covers boot modes, event handling, power management, and timing specifications.
| Core frequency | 600 MHz |
|---|---|
| On‑chip memory | 328 KB |
| Arithmetic units per core | Two 16‑bit MACs, two 40‑bit ALUs, four 8‑bit video ALUs, 40‑bit shifter |
| I/O voltage levels | 2.5 V and 3.3 V |
| Package options | 256‑ball CSP‑BGA (two sizes) and 297‑ball PBGA |
| Timers/counters | 12 general‑purpose 32‑bit with PWM |
| Watchdog timers | Dual |
| GPIO flags | 48 programmable |
| PLL multiplication range | 0.5×‑64× |
It provides 328 KB of on‑chip memory.
It has 12 general‑purpose 32‑bit timers/counters with PWM capability.