The document describes the features and characteristics of the PKD01 monolithic peak detector with reset-and-hold mode from Analog Devices, including reliability, low cost, high slew rate, low droop rate, low zero-scale error, digitally selected hold and reset modes, etc.
The PKDO1 is a monolithic peak detector with reset‑and‑hold capability, offering high slew rate, low droop, and selectable hold and reset modes. It integrates a transconductance amplifier, an uncommitted comparator, and logic‑compatible TTL/CMOS inputs, making it suitable for precision peak‑detect applications.
The document lists detailed electrical characteristics, absolute maximum ratings, ordering options, pin configuration, typical performance graphs, and mechanical dimensions. It also includes wafer‑test limits and notes on ESD sensitivity, providing engineers with the data needed for design and verification.
| Slew Rate | 0.5 V/µs |
|---|---|
| Zero‑Scale Error | 4 mV (typical) |
| Input Offset Voltage | 2‑3 mV (typical) |
| Droop Rate (25 °C) | 0.01 mV/ms (max) |
Logic “1” input voltage is 2 V and logic “0” input voltage is 0.8 V.
Typical input offset voltage is about 2 mV to 3 mV.