This document introduces the Analog Devices' dual-matched NPN transistor MAT12 Rev. 0. The product features very low voltage noise, excellent current gain match, low offset voltage, outstanding offset voltage drift, high gain bandwidth product, and more.
The MAT12 is a dual, NPN‑matched transistor pair designed for ultra‑low‑noise audio applications. It offers very low voltage noise, tight current‑gain matching, and low offset voltage, making it suitable for balanced designs, current mirrors, and bias circuits.
The document includes sections on features, pin configuration, electrical characteristics, absolute maximum ratings, thermal resistance, typical performance curves, application examples such as a fast logarithmic amplifier, mechanical dimensions, and ordering information.
| Voltage noise density (100 Hz) | 1 nV/√Hz |
|---|---|
| Typical current gain (hFE) at 1 mA | ≥600 |
| Collector‑to‑Emitter breakdown voltage (BVCEO) | 40 V |
| Maximum collector current (IC) | 20 mA |
| Storage temperature range | -65 °C to +150 °C |
The datasheet lists a maximum collector current of 20 mA.
The typical voltage‑noise density is 1 nV/√Hz at 100 Hz.
The collector‑to‑emitter breakdown voltage is specified as 40 V.
The typical current‑gain exceeds 600 at a collector current of 1 mA.