The ADCMP561/ADCMP562 are high-speed PECL comparators with 700 ps propagation delay, 75 ps propagation delay dispersion, -2.0 V to +3.0 V input common-mode range, robust input protection, differential latch control, internal latch pull-up resistors, power supply rejection ratio greater than 85 dB, 700 ps minimum pulse width, 1.5 GHz equivalent input rise time bandwidth, typical output rise/fall time of 500 ps, ESD protection > 4kV HBM, >200V MM programmable hysteresis.
The ADCMP561 and ADCMP562 are dual high‑speed PECL comparators featuring differential PECL‑compatible outputs, 700 ps propagation delay, and programmable hysteresis (ADCMP562). They operate over a wide input common‑mode range of –2.0 V to +3.0 V and include internal latch control for tracking or sample‑and‑hold modes.
These devices are suited for automatic test equipment, high‑speed instrumentation, line receivers, clock drivers, and other applications requiring fast threshold detection. Detailed electrical characteristics, pin descriptions, and typical performance graphs are provided for design engineers.
| Propagation delay (typical) | 700 ps |
|---|---|
| Input common‑mode voltage range | -2.0 V to +3.0 V |
| Power supply rejection ratio | > 85 dB |
| Minimum pulse width | 700 ps |
| Positive supply current @ +5.0 V | 3.2 mA |
| Operating temperature (ambient) | -40 °C to +85 °C |
| Output rise time (10‑90 %) | 550 ps |
The typical propagation delay is 700 ps from input to output.
They accept input common‑mode voltages from –2.0 V to +3.0 V.
The devices operate from –40 °C up to +85 °C ambient temperature.
They provide a power supply rejection ratio greater than 85 dB.