This document is an errata sheet for MAXQ622 revision B1 components, describing the abnormal behaviors of these components in certain situations. The errata sheet provides workarounds. The main issues include the watchdog timer reset locking the IC in reset and flash program/erase operations failing in clock-divided mode.
The document provides a list of errata that affect the MAXQ622 B1 revision, describing the observed behavior and recommended work‑arounds for each issue. It covers problems ranging from watchdog timer resets to flash programming failures, memory protection faults, power‑supply anomalies, and instruction‑execution errors.
Each entry includes a brief description of the symptom, the conditions under which it occurs, and a practical mitigation strategy that designers can apply to avoid or correct the problem in their designs.
The watchdog timer reset locks the IC in reset, requiring a power cycle to recover.
Set the system clock to divide‑by‑1 (non‑divided) mode before invoking flash write or erase functions.
Avoid using memory protection or avoid debugging in the upper memory region.
Set the FRCVDD control to logic‑low under the condition where Vpp < Vpps‑0.5 V.