Intel Manuals

Intel's 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-board during subassembly test; in-system during final test; and in-system after sale. The 28F020 increases memory flexibility, while contributing to time and cost savings. The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of eight bits. Intel's 28F020 is offered in 32-

MCS@51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS are microcontrollers optimized for control applications. They have high performance, internal timers/event counters, a 2-level interrupt priority structure, 32 I/O lines, and 64KB external program memory space, among other features.

The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media. The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V power supply.

This document provides the user's guide for Intel® Server Board S5000VSA, intended for technically qualified assemblers. The document includes detailed information about the product, including disclaimers, technical specifications, and features.

This is an Intel ® Boot Agent User's Guide

This is an article about P85C220-10

80960JD is a 32-bit embedded microprocessor. It is pin/code compatible with all 80960Jx processors, has high-performance embedded architecture, two caches, high bandwidth burst bus and many new instructions.

This data sheet provides details on the features of the 21555 non-transparent PCI-to-PCI bridge, including compliance with the PCI local Bus Specification, Revision 2.2, PCI Power Management, Vital Product Data (VPD) support, CompactPCI Distributed Hot-Swap support, 3.3-V operation with 5.0-V tolerant I/O, selectable asynchronous or synchronous primary and secondary interface clocks, concurrent primary and secondary bus operation, Advanced Configuration Power Interface (ACPI) specification, PCI Bus Power Management specification, queuing of multiple transactions in either direction, 256 bytes of posted write (data and address) buffering in each direction, 256 bytes of read data buffering in each direction, four delayed transaction entries in each direction, two dedicated I2O delayed transaction entries, two sets of standard PCI Configuration registers corresponding to the primary and secondary interface; each set is accessible from either the primary or secondary interface, direct offset address translation for downstream memory and I/O transactions, hardware enable for secondary bus central functions, IEEE Standard 1149.1 boundary-scan JTAG interface, four primary interface base address configuration registers for downstream forwarding, with size and prefetchability programmable for all four address ranges, three secondary interface address configuration registers specifying local address ranges for upstream forwarding, with size and prefetchability programmable for all three address ranges.

Intel StrataFlash® Embedded Memory (P30) 1-Gbit P30 Family Datasheet is the latest generation of Intel embedded flash memory devices. The product features high density, high speed, low cost, support for code and data storage, and reliable security options.

This document provides information about the features and characteristics of Intel's 8XC152JA, JB, JC, JD Universal Communication Controller, including differentiation from other brands, product details, and technical specifications.

M80C186XL20 is a 16-bit high-integration embedded processor from Intel, with low power and full static version of M80C186.

This document introduces Intel's Word-Wide FlashFile™ memory family, which provides high-density, low-cost, non-volatile, read/write storage solutions for a wide range of applications. The memory family has a symmetrically-blocked architecture, flexible voltage, and extended cycling life, which makes it suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities can improve system performance.

Intel® 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High-Integration Embedded Processors Datasheet is a 16-bit high integration embedded microprocessor from Intel, which features static operation, true CMOS inputs and outputs, low power consumption and easy expansion

This document provides an overview of the features and characteristics of the Intel 82503 Dual Serial Transceiver (DST) product, including its Ethernet interface to both 802.3 10BASE-T and AUI, automatic or manual port selection, Manchester Encoder-Decoder and Clock Recovery, no glue interface to industry-standard LAN controllers, diagnostic loopback, low power modes, etc.