IDT Manuals

This document introduces IDT's DSC-3873/07 128K x 8 advanced high-speed CMOS static RAM, and its features such as reduced noise, equal access and cycle times, low power consumption, etc.

The document introduces a high-speed 3.3V 32K x 18 synchronous pipelined dual-port static RAM with a 3.3V or 2.5V interface, and provides detailed information about its features and characteristics.

DSC-5670/3 is a high-speed asynchronous dual-port static RAM produced by IDT company. It has dual-port memory cells that support concurrent access to the same memory location. It supports 3.3V/2.5V power supply, provides a rapid write mode, supports depth expansion, and supports a 36-bit or wider data bus.

qs3vh2861 is a high-bandwidth switch chip produced by idt company. it has a 10-bit flow-through pinout, 25 ohm switch impedance and 1.35ns propagation delay. it is ideal for line matching and low noise environments. the chip adopts active low enable control. in the on state, it can pass 5v voltage. in the off state, it can isolate 5v voltage, making it an ideal choice for high-speed data buses.

DSC-6223/4 CODEC is a 4-channel CODEC chip produced by IDT. It supports A/µ-law and linear coding, meets ITU-T G.711-G.714 standards, has programmable digital filters, supports two programmable PCM buses, and MPI control interface, broadcast mode, 7 SLIC signaling pins, fast hardware ring trip mechanism, 2 programmable tone generators, two programmable chopper clocks, selectable master clock frequency, advanced test functions, 300 Ω AC high analog drive capability, 3 V digital I/O, +3.3 V single power supply, low power consumption, and -40°C to +85°C operating temperature range.

The IDT71V3556 and IDT71V3558 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

The IDT7005S/L high-speed 8K x 8 Dual-Port Static RAM has true Dual-Ported memory cells which allow simultaneous access of the same memory location, with high-speed access and low-power operation. It can be expanded using the Master/Slave select when cascading more than one device.

The FCT574 is an 8-bit register built using an advanced dual metal CMOS technology.

The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

This document introduces the IDT71V016 64K x 16 high performance static random access memory (SRAM). This product is manufactured using IDT's high-performance, high-reliability CMOS technology. This technology combined with innovative circuit design techniques provides a cost-effective solution for high-speed memory needs. The IDT71V016 has a 5ns output enable pin with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and operation is from a single 3.3V supply. This product uses fully static asynchronous circuitry, requiring no clocks or refresh for operation. The product is packaged in a JEDEC standard 44-pin plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA package.

IDT71P72204 is a 18Mb dual-channel QDR™II SRAM chip produced by IDT company. The chip has 18Mb storage capacity, supports DDR (double data rate) multiplexed address bus, supports 2-Word Burst, and can achieve 2 data ports simultaneously reading and writing operations, providing up to 4 data bytes per clock cycle. Data transfer rate.

This document describes the features and characteristics of the IDT7008S/L high-speed 64K x 8 dual-port static RAM, including expandable data bus width, support for semaphore signaling, fully asynchronous operation, and low-power operation.

The IDT54/74FCT139T/AT/CT is a fast CMOS 1-OF-4 decoder with enable. It features low input and output leakage, CMOS power levels, true TTL input and output compatibility, high drive outputs, and meets or exceeds JEDEC standard 18 specifications.