Monitor manuals, page 14
National semiconductor DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display handbook
The DS90CF383 is a +3.3V LVDS transmitter from National Semiconductor Corporation that supports a 24-bit Flat Panel Display (FPD) Link, and uses a 65 MHz transmit clock to sample 28 bits of input data per cycle and transmit it at a rate of 455 Mbps per LVDS data channel.
National semiconductor DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display handbook
DS90CF386/DS90CF366 is a LVDS receiver chip produced by TI company. It can convert four LVDS data streams (up to 2.38 Gbps throughput or 297.5 megabytes/second bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL)
National semiconductor DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display handbook
National semiconductor DS90CF383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display handbook
The DS90CF383B is a programmable LVDS transmitter that converts 28 bits of CMOS/TTL data into four LVDS data streams. It supports a transmit clock frequency of 65 MHz and can transmit 24 bits of RGB data and 3 bits of LCD timing and control data at a rate of 455 Mbps per LVDS data channel. The DS90CF383B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
National semiconductor DS90CF363 +3.3V LVDS Transmitter 18-Bit Flat Panel Display handbook
The DS90CF363 is a 3.3V LVDS transmitter, 18-bit Flat Panel Display (FPD) link - 65 MHz. It converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
Apple Multiple Scan 17 Display User Guide
This document is the user's guide for the Apple Multiple Scan17 Display, released by Apple Inc. It describes the features and characteristics of the product.
Apple Multiple Scan 15 Display User Guide
This manual introduces the features and usage of Apple Multiple Scan 15 Display 15-inch CRT (13.3-inch diagonal viewable image size).
AppleVision display user manual
Introduce how to use the Monitors & Sound control panel to set the color, resolution, sound, geometry, and other controls for Mac system display
Apple Multiple Scan 14 Display User Guide
Apple Multiple Scan 14 Display User’s Guide 14-inch CRT (12.4-inch diagonal viewable image size)
Apple Multiple Scan 1705 Display User Guide
Apple Multiple Scan 1705 Display User's Guide is a product user manual released by Apple Computer, Inc. about Apple Multiple Scan 1705 Display.
Apple Multiple Scan 15AV Display User Guide
This manual describes the features and operation of the Apple Multiple Scan 15AV display
AppleVision Display AppleVision 850 850AV User manual
This manual explains how to set up and connect your AppleVision 850 and AppleVision 850AV monitors, as well as important safety information.
Apple ColorSync Display User manual
This manual describes the features and use of Apple ColorSync Display K.
Apple Studio display (17 inches CRT) user manual
This manual describes how to use the 17-inch CRT Studio Display.
apple Setting Up Your Studio Display 17-inch CRT (16-inch diagonal viewable image size) USER'S MANUAL
This document describes how to set up Apple Studio Display 17-inch CRT display