This guide explains the Branch Target Buffer (BTB) operation, advantages, and potential errors in the Analog Devices ADSP-TS101 TigerSHARC DSP.
This Engineer-to-Engineer guide discusses the Branch Target Buffer (BTB) in the TigerSHARC DSP ADSP-TS101. It explains how the BTB works, when it provides advantages, and potential errors that may occur. The guide covers the operation of the BTB, which is a 4-way set-associative cache for branch instructions, and provides guidance on optimizing performance by avoiding conflicts in the BTB.
The document details how the BTB reduces clock cycle delays when executing branch instructions, specifically noting that it can reduce delay to zero cycles if the branch condition is true repeatedly. It also provides specific instructions on how to avoid compiler warnings regarding two branch instructions within the same 4-word memory space, including the use of the 'NP' suffix to force non-prediction.
| Pipeline Depth | 8 stages |
|---|---|
| BTB Associativity | 4-way set-associative |
| BTB Entry Depth | 128 entries |
| BTB Replacement Policy | Least Recently Used |
| BTB TAG Storage | 4-word address |
If a branch instruction is executed repeatedly with the condition true, the BTB allows the program controller to fetch the target address immediately, reducing the delay to zero clock cycles.
It is advantageous when the same branch instruction is executed repeatedly and the branch condition is true every time, such as in loops.
The compiler will issue a warning because the BTB cannot distinguish between the two instructions as they share the same TAG value.
You can add the suffix 'NP' to the end of the instruction to force the non-prediction of the branch.