Analog Devices AD9852 Digital Synthesizer Data Sheet

This datasheet details the AD9852 digital synthesizer, a highly integrated DDS device with internal D/A converters for generating stable, programmable…


Analog Devices AD9852 Digital Synthesizer Data Sheet - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
41
File format
PDF
File size
762 KB
Published
17 October, 2026
Updated
17 October, 2026
Model
AD9852
MD5 checksum
B3B67333853FB05F80FBBB0C510AF288

About this manual

The AD9852 is a highly integrated digital synthesizer that uses advanced Direct Digital Synthesis (DDS) technology coupled with an internal high-speed, high-performance D/A converter. It generates a highly stable frequency-, phase-, and amplitude-programmable cosine output suitable for use as an agile local oscillator (LO) in communications, radar, and test and measurement equipment. The device features a 48-bit frequency resolution and can generate output signals at frequencies up to 150 MHz.

What's inside

  • Features
  • Applications
  • Functional Block Diagram
  • General Description
  • Specifications
  • Absolute Maximum Ratings
  • Pin Configuration
  • Modes of Operation
  • Programming the AD9852
  • Ordering Guide

Specifications

Internal System Clock Frequency Range (Multiplier Enabled)20 to 300 MHz
External Reference Clock Frequency Range (Multiplier Enabled)5 to 75 MHz
DAC Resolution12 Bits
Output Update Speed300 MSPS
Full-Scale Output Current5 to 20 mA
Wideband SFDR (1 MHz to 20 MHz)58 dBc
Narrow-Band SFDR (10 MHz A OUT ±1 MHz)83 dBc
Operating Temperature Range-40°C to +85°C

Frequently asked questions

What is the tuning resolution of the AD9852?

The device provides 48-bit frequency resolution, achieving 1 μHz tuning resolution with a 300 MHz SYSCLK.

What is the maximum output signal frequency?

The circuit architecture allows the generation of output signals at frequencies up to 150 MHz.

Does the AD9852 include a reference clock multiplier?

Yes, it includes a programmable 4× to 20× REFCLK multiplier circuit to generate the 300 MHz system clock.

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