The ST40 is a 32-bit RISC (reduced instruction set computer) microprocessor. It includes separate instruction and operand caches. The operand caches support both copy-back and write-through modes. The 16-bit fixed-length instruction set gives the architecture extremely good code density. The ST40 core products are grouped into series. These series can be distinguished by the following features. • The associativity of the cache architecture. • The presence of index and RAM modes in the cache architecture. • The presence of a floating point unit (FPU). This provides hardware support for scalar and vector floating point computation. • The presence of a memory management unit (MMU). This provides hardware support for translation and protection of parts of the address space. It incorporates a 64 entry unified translation lookaside buffer (TLB) and a 4 entry instruction TLB which caches entries from the unified TLB without software intervention. • The width of physical addressing used on the STBus. Earlier ST40 cores support 29-bit physical addressing. Newer ST40 cores can also support 32-bit physical addressing.