The 74F109 is a double JK positive edge-triggered flip-flop released by Fairchild Semiconductor Corporation
This document is a datasheet for the Fairchild Semiconductor 74F109, a dual high-speed, completely independent transition clocked JK flip-flop. The device allows operation as a D-type flip-flop by connecting the J and K inputs and features asynchronous clear and set inputs that are independent of the clock.
The datasheet provides comprehensive technical data including truth tables, logic symbols, connection diagrams, and absolute maximum ratings. It details DC and AC electrical characteristics such as propagation delay, setup time, and hold time, along with physical dimensions for three available package types: SOIC, SOP, and PDIP.
| Number of Flip-Flops | 2 |
|---|---|
| Maximum Clock Frequency | 100 MHz |
| Propagation Delay (Typical) | 3.8 ns |
| Package Types | SOIC, SOP, PDIP |
Yes, it can operate as a D-type flip-flop by connecting the J and K inputs.
No, the Clear and Set inputs are independent of the clock.