National Semiconductor 54F/74F109 Dual JK Flip-Flop Datasheet

About this manual

This document provides a comprehensive technical overview of the National Semiconductor 54F/74F109, a high-speed dual JK positive edge-triggered flip-flop. It details the device's logic operations, including its ability to function as a D flip-flop, and lists various ordering codes for different package types such as DIP, SOIC, and ceramic carriers.

The datasheet includes absolute maximum ratings, DC and AC electrical characteristics for both commercial and military temperature ranges, and detailed physical dimensions for all available packages. It also presents truth tables and connection diagrams to assist in circuit design and implementation.

What's inside

• General Description
• Features
• Ordering Code
• Logic Symbols
• Connection Diagrams
• Truth Table
• Absolute Maximum Ratings
• DC Electrical Characteristics
• AC Electrical Characteristics
• Physical Dimensions

Specifications

Frequently asked questions

Can the 54F/74F109 operate as a D flip-flop?

Yes, it can operate as a D flip-flop by connecting the J and K inputs.

Are the Clear and Set inputs dependent on the clock?

No, the Clear and Set inputs are independent of the clock.

What is the minimum ESD protection rating?

The device has a guaranteed minimum ESD protection of 4000V.