This document is the manual for TigerSHARC Embedded Processor ADSP-TS203S Rev. D.
The ADSP-TS203S is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. Operating at 500 MHz, it features a 2.0 ns instruction cycle time and supports floating-point and fixed-point processing. The processor combines very wide memory widths with dual computation blocks to set a new standard of performance for digital signal processors.
| Operating Frequency | 500 MHz |
|---|---|
| Instruction Cycle Time | 2.0 ns |
| Internal Memory | 4M bits |
| Package Type | 576-ball BGA |
| Internal Memory Bandwidth | 28 GBytes/s |
| Floating-Point Formats | IEEE 32-bit and 40-bit |
The processor operates with a 2.0 ns instruction cycle rate.
The processor includes 4M bits of internal on-chip DRAM memory.
The package measures 25 mm × 25 mm.