Implementing an Ogg Vorbis Decoder on SHARC Processors EE-320 Application Note

About this manual

The document describes a technical approach to implementing an Ogg Vorbis decoder in real-time on Analog Devices SHARC processors, specifically the ADSP-21364 and ADSP-21369 models. It utilizes the EZ-KIT Lite hardware platform and VisualDSP++ development tools for software implementation.

The guide outlines a workflow that begins with validating open-source Vorbis Library 1.1.2 code using Microsoft Visual C++. This validated code is then ported to SHARC processors, leveraging specific architectural features such as the I/O processor, DMA controllers, and internal memory blocks to optimize performance for audio processing tasks.

What's inside

• Introduction
• Ogg Vorbis Codecs
• Real-Time Implementation
• Using Visual C++ as a Reference Platform
• Architectural Advantages of SHARC Processors
• High Speed and I/O Processor Features
• On-chip Memory Blocks
• External Port Interfaces
• Parallel Port Interfaces
• Optimization

Frequently asked questions

Which SHARC processors are used for the Ogg Vorbis decoder implementation?

The decoder is implemented on the ADSP-21364 and ADSP-21369 SHARC processors.

What development tools are used for software implementation?

The VisualDSP++ development tools are used for the software development of the application.

What version of the Vorbis Library is referenced in this note?

The document uses the Vorbis Library 1.1.2 (libvorbis) source code.