ADSP-21160M/ADSP-21160N is a high-performance 32-bit DSP chip from Analog Devices. It uses a Super Harvard architecture with 4 independent buses for dual data fetch, instruction fetch, and non-intrusive zero-overhead I/O. The chip is also backward compatible with ADSP-2106x DSP chips and has a single-instruction, multiple-data (SIMD) computational architecture, an integrated I/O processor, a 4M-bit on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG).
This document describes the ADSP-21160x family of high-performance 32-bit SHARC digital signal processors (DSPs). The family includes two members: the ADSP-21160M, fabricated in a 0.25 micron CMOS process with an 80 MHz instruction rate, and the ADSP-21160N, fabricated in a 0.18 micron CMOS process with a 100 MHz instruction rate. Both processors feature a Super Harvard architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O.
| Instruction Rate (ADSP-21160N) | 100 MHz |
|---|---|
| On-chip SRAM Size | 4 Mbits |
| Package Type | 400-ball PBGA |
The ADSP-21160N offers higher performance (100 MHz vs 80 MHz) and lower power consumption than the ADSP-21160M.
Yes, it is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD mode.