This application note provides critical layout guidelines to avoid noise coupling as well as proper grounding techniques for the ADP1046 digital power controller.
This document is an application note titled "Layout Considerations for Digital Power Management (ADP1046)" published by Analog Devices. It addresses critical layout guidelines to avoid noise coupling and establish proper grounding techniques for the ADP1046, a secondary side controller featuring analog-to-digital converters and integrated communication.
The text details modes of noise coupling, including common impedance, capacitive, inductive, and radiation, offering specific mitigation strategies. It provides detailed instructions on the placement of the ADP1046 relative to switching elements and sensing points, as well as specific requirements for power traces, decoupling capacitors, and ground connections (PGND, AGND, DGND). The document includes recommendations for trace widths, component placement, and the use of daughter cards for prototyping.
| ADC Data Conversion Rate | 1.6 MHz and 25 MHz |
|---|---|
| Recommended Trace Width for VS3+/CS2+ | 15 mils to 20 mils |
| Recommended Trace Width for CS1 | 30 mils |
| CS1 Pin Capacitor Value | 1 nF |
| VCORE to DGND Capacitor | 330 nF/X7R |
| Absolute Maximum Rating for CS1 Pin | 3.3 V |
The four main causes are common impedance coupling, capacitive coupling, inductive coupling, and radiation.
A 0.1% resistor is recommended because the tolerance of the internal clock frequency is directly proportional to the accuracy of the RES pin resistor.