The document discusses timing constraints for the AD7878, a 12-bit A/D converter with a FIFO memory. It explains that while synchronous clock interfacing is recommended in the data sheet, it is not suitable for every microprocessor and may reduce throughput. An alternative asynchronous method is presented that allows operation at any sampling frequency up to 100 kHz.
| Resolution | 12-bit |
|---|---|
| FIFO Memory | 8-word |
| Maximum Sampling Frequency | 100 kHz |
The device can operate at any sampling frequency up to the maximum of 100 kHz.
Synchronous interfacing is not suitable for every microprocessor and may reduce throughput depending on the clock frequency.