This application note describes how to interface the ADSP-BF535 Blackfin® processor to high-speed converters, such as the AD9860/2, over the external memory bus.
This document provides technical guidance on connecting the Analog Devices ADSP-BF535 Blackfin processor to high-speed analog-to-digital (ADC) and digital-to-analog (DAC) converters, such as the AD9860/2, via the External Memory Bus. It addresses the specific challenge that the ADSP-BF535 lacks a dedicated Parallel Peripheral Interface (PPI) found in other Blackfin models, necessitating the use of an External Bus Interface Unit (EBIU) and external logic for control.
The note details a design approach utilizing a low pin-count Programmable Array Logic (PAL), Complex Programmable Logic Device (CPLD), or FPGA to manage the interface. This logic performs control functions and data latching between the converter and the processor's asynchronous external memory bus. The document outlines design goals, such as minimizing external logic and avoiding FIFOs, and discusses trade-offs regarding DMA controllers and memory multiplexing.
| Core Clock Frequency | 300MHz |
|---|---|
| Maximum System Clock (SCLK) | 133MHz |
| On-board Memory Size | 308K bytes |
| PCI Interface Speed | 33MHz |
| Maximum Transfer Bandwidth (via PCI) | 132MB/sec |
| Maximum SCLK Transfer Rate (No FIFO) | 13.3M words/second |
No, unlike the ADSP-BF531/BF532/BF533, the ADSP-BF535 does not have a dedicated PPI to connect directly to high-speed converters.
The document recommends using a low pin count Programmable Array Logic (PAL), Complex Programmable Logic Device (CPLD), or FPGA.
No, simultaneous access is not possible because there is only one memory interface that can do a read or a write at a time.