The ADAU1328 is a high performance, single-chip codec that provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs). It features a PLL clock generator or direct master clock, supports 24 bits and 8 kHz to 192 kHz sample rates, and has a low EMI design.
The document describes the ADAU1328, a high-performance single-chip audio codec utilizing Analog Devices' patented multibit sigma-delta (Z-A) architecture. It provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with single-ended output.
| ADC Resolution | 24 Bits |
|---|---|
| Dynamic Range (No Filter) | 98 to 102 dB |
| Total Harmonic Distortion + Noise | -96 to -87 dB |
| Supply Voltage (DVDD/AVDD) | 3.0V to 3.6V |
| Master Clock Frequency (PLL mode) | 6.9 MHz to 13.8 MHz |
| Input Sample Rate Support | 8 kHz to 192 kHz |
The ADAU1328 is a high performance, single-chip codec that provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with single-ended output.
The ADAU1328 operates from 3.3 V digital and analog supplies.
The device supports sample rates up to 192 kHz.