PhaseLink PLL502-02 Low Phase Noise VCXO Datasheet

The PLL502-02 is a low cost, high performance, low phase noise VCXO, providing less than -130dBc at 10kHz offset in the 24MHz to 50MHz operating range.


PhaseLink PLL502-02 Low Phase Noise VCXO Datasheet - cover page
Brand
PhaseLink
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
4
File format
PDF
File size
174 KB
Published
07 June, 2012
Updated
30 September, 2023
MD5 checksum
28EF2A3CF00FF28E1841EED289D1B7D6

About this manual

The PhaseLink PLL502-02 is a low cost, high performance, low phase noise VCXO designed for the 24MHz to 50MHz operating range. It features an integrated variable capacitor and provides less than -130dBc phase noise at a 10kHz offset.

The device operates from a single +3.3V supply and is available in an 8-Pin SOIC package. It offers selectable High Drive (30mA) or Standard Drive (10mA) output currents to suit various application requirements.

What's inside

  • Features
  • PIN Configuration
  • Description
  • Output Range
  • Block Diagram
  • PIN Descriptions
  • Absolute Maximum Ratings
  • DC Specifications
  • AC Electrical Specifications
  • Ordering Information

Specifications

Operating Frequency Range24MHz to 50MHz
Input Crystal Frequency12 to 25 MHz
Operating Voltage+3.3V
Output Drive Current (High)30 mA
Output Drive Current (Standard)10 mA
Pull Range+/- 250 ppm typ.
RMS Period Jitter3ps period (1 sigma)
Phase Noise @ 10kHz offset-130 dBc/Hz

Frequently asked questions

What is the typical phase noise performance?

The device provides less than -130dBc at a 10kHz offset.

What is the stabilization time from power valid?

The VCXO stabilization time is typically 10 ms.

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