PhaseLink PLL500-17 handbook

Update: 28 September, 2023

The PLL500-17 is a low-cost, high-performance, and low-phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources.


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MD5 Checksum: 01350AA71E2936506053E4EC5E83FAD7

Publication date: 04 June, 2012

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PDF Link: PhaseLink PLL500-17 handbook PDF

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