The PLL500-17 is a low-cost, high-performance, and low-phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources.
The PLL500-17 is a low‑phase‑noise voltage‑controlled crystal oscillator (VCXO) that operates from 17 MHz to 36 MHz. It offers excellent jitter performance (2.5 ps RMS) and very low phase noise, making it suitable for precision timing applications.
The document lists detailed electrical specifications, pin configurations for 8‑Pin SOIC and 6‑Pin SOT‑23 packages, die‑pad layout, and ordering information. Key parameters such as supply voltage, temperature range, pull‑range linearity and output drive capability are provided for designers.
| Frequency range | 17 MHz to 36 MHz |
|---|---|
| Phase noise @10 kHz offset | -130 dBc/Hz |
| RMS period jitter | 2.5 ps |
| Supply voltage (VDD) | 4.6 V |
| Operating temperature range | -40 °C to 85 °C |
| Pull‑range linearity | 5 % |
| Output drive capability | 12 mA |
| Package options | 8‑Pin SOIC, 6‑Pin SOT‑23 |
The PLL500-17 operates from 17 MHz to 36 MHz.
It achieves –130 dBc/Hz phase noise at a 10 kHz offset.
The RMS period jitter is 2.5 ps.
The device is offered in 8‑Pin SOIC and 6‑Pin SOT‑23 packages.