PhaseLink PLL520-38/39 Handbook

The PLL520-38/-39 is a low phase noise VCXO integrated circuit designed for pulling high frequency fundamental crystals from 65MHz to 130MHz. It features low injection power, PECL or LVDS output, integrated variable capacitors, and supports 2.5V or 3.3V power supply. It is ideal for applications with demanding timing requirements.


PhaseLink PLL520-38/39 Handbook - cover page
Brand
PhaseLink
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
7
File format
PDF
File size
243 KB
Published
07 May, 2012
Updated
28 September, 2023
MD5 checksum
3995663824B6EB822BDA553B2DC8947E

About this manual

The PLL520‑38/39 family are low‑phase‑noise voltage‑controlled crystal oscillators (VCXOs) designed for fundamental crystals from 65 MHz to 130 MHz. They offer selectable PECL (PLL520‑38) or LVDS (PLL520‑39) outputs and operate from 2.5 V or 3.3 V supplies.

The document lists detailed pin functions, absolute maximum ratings, crystal and jitter specifications, as well as LVDS and PECL electrical characteristics. Package options include a 16‑pin TSSOP or a 3 × 3 mm QFN, and ordering information is provided for commercial and industrial temperature grades.

What's inside

  • Features
  • Pin Descriptions
  • Electrical Specifications
  • Jitter Specifications
  • Phase Noise Specifications
  • LVDS Electrical Characteristics
  • PECL Electrical Characteristics
  • Package Information
  • Ordering Information

Specifications

Supply Voltage (Voo) minimum4.6 V
Operating Voltage (Voo) range2.97 V – 3.63 V
Output Differential Voltage (LVDS)247 mV – 454 mV

Frequently asked questions

What supply voltage is required for the PLL520‑38/39?

The device requires a minimum supply voltage of 4.6 V (Voo).

What package options does the PLL520‑38/39 come in?

It is available in a 16‑pin TSSOP or a 3 × 3 mm QFN package.

What is the ambient operating temperature range?

The ambient operating temperature is guaranteed from –40 °C to 85 °C.

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