The document addresses the need for carefully controlled, high-voltage programming power in digital systems utilizing flash memories. It details how to derive and control these voltages within tight tolerances to prevent device destruction during chip-erase and reprogramming operations.
Several circuit designs are presented, including a basic voltage supply using the LT1072 switching regulator for 12V or 12.75V outputs, and high repetition rate supplies utilizing continuous regulation with scaling loops. The text also covers specific requirements for EEPROMs (such as rise time constraints) and includes a circuit for generating 4-20mA current loop signals from 5V systems.
| Flash memory full chip erase time | 1 second |
|---|---|
| Maximum Vpp excursion voltage | 14V |
| EEPROM Vpp pulse rise time requirement | 600us |
Vpp excursions beyond 14V for 20ns or longer will destroy the device.
The circuit prevents spurious overshoots during power-up or down, which could otherwise destroy the memory.