The 100331 is a low power triple D flip-flop with true and complement outputs, a Common Clock (CPC) and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down resistors.
The 100331 is a low‑power triple D‑type edge‑triggered flip‑flop that includes three master/slave stages with true and complementary outputs, individual clock, set and clear inputs, and master set/master reset controls. It offers 35% power reduction compared with the 100131 and includes 2000 V ESD protection.
Key specifications include a supply voltage range of –5.7 V to –4.2 V, output high current of 50 mA, toggle frequency up to 400 MHz, propagation delays around 0.5 ns, and operation over a temperature range of –55 °C to +125 °C. The device is offered in 24‑lead DIP and 24‑lead Quad Cerpak packages and meets military‑grade storage temperature limits of –65 °C to +150 °C.
| Supply Voltage (Vee) | -5.7 V to -4.2 V |
|---|---|
| ESD Protection | < 2000 V |
| Output HIGH Current | 50 mA |
| Operating Temperature Range | -55 °C to +125 °C |
| Storage Temperature Range | -65 °C to +150 °C |
The device is specified for a supply voltage (Vee) between –5.7 V and –4.2 V.
The 100331 provides ESD protection of less than 2000 V.