The Intel® XScale™ Microarchitecture User’s Manual provides information on the features and characteristics of the PXA255 processor.
This manual provides an overview of the Intel XScale microarchitecture as implemented in the PXA255 processor, including high‑level architecture, cache structures, and power‑management features. It also describes the programming model, ARM compatibility, and extensions such as the DSP coprocessor.
Further sections cover the register set (CP15, CP14), performance monitoring, software debugging via JTAG, and detailed timing information for instructions, branches, and memory operations. The document includes errata information and legal notices.
| Architecture Compatibility | ARM |
|---|---|
| Performance Monitoring Feature | Clock Counter (CCNT) |
| Power Management | Supported |
Current characterized errata are available on request.
The BTB handles branch target prediction as described in the BTB operation section.
The Instruction Cache can be disabled as described in the "Instruction Cache is Disabled" section.
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