Blackfin® Embedded Processor ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. A is a high-performance, high-integration embedded processor. It uses a RISC-like instruction set, has 2 16-bit MAC units, 2 40-bit ALU units, 4 8-bit video ALU units, and a 40-bit shifter, supporting speeds of up to 600MHz.
This handbook introduces the ADSP-BF531, ADSP-BF532 and ADSP-BF533 Blackfin processors, members of the Blackfin family that combine a dual‑MAC signal‑processing engine with a RISC‑like core and SIMD multimedia capabilities. It describes the portable low‑power architecture, dynamic power management, and the system‑on‑chip integration that make these devices suitable for digital communication and consumer multimedia applications.
The document also covers the rich set of on‑chip peripherals—including UART, SPI, two SPORT ports, timers with PWM, a real‑time clock, watchdog timer and parallel peripheral interface—along with memory organization, boot modes, event handling, and the core and system interrupt controllers. Detailed memory maps, timing specifications and pin descriptions are provided for hardware designers.
| Maximum core frequency | 400 MHz (BF531/BF532), 600 MHz (BF533) |
|---|---|
| On‑chip memory size | Up to 148 KB (16 KB instruction SRAM/Cache, 64 KB instruction SRAM, 32 KB data SRAM/Cache, 32 KB data SRAM, 4 KB scratchpad SRAM) |
| MAC units | Two 16‑bit MACs |
| ALU units | Two 40‑bit ALUs and four 8‑bit video ALUs |
| DMA controller | 12‑channel DMA controller |
| Timers with PWM | Three timer/counters with PWM support |
| UART with IrDA support | UART port supporting IrDA® |
The BF531 and BF532 run up to 400 MHz, while the BF533 runs up to 600 MHz.
Each device provides up to 148 KB of on‑chip memory, including instruction SRAM, data SRAM, and a 4 KB scratchpad.
Integrated peripherals include a UART with IrDA, an SPI port, two SPORT serial ports, four general‑purpose timers (three with PWM), a real‑time clock, a watchdog timer and a parallel peripheral interface.
It uses a two‑stage event controller consisting of a Core Event Controller (CEC) and a System Interrupt Controller (SIC) that manage emulation, reset, NMI, exceptions and interrupt events.