Update: 28 September, 2023
This document is a preliminary data sheet for the 2G bits DDR2 SDRAM product. The product features a double-data-rate architecture, allowing for two data transfers per clock cycle. The high-speed data transfer is achieved through a 4-bit prefetch pipelined architecture. Bi-directional differential data strobe (DQS and /DQS) is used to transmit/receive data and capture data at the receiver. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The product is available in two organizations: 64M words × 4 bits × 8 banks or 32M words × 8 bits × 8 banks. It supports multiple data rates, page sizes, burst lengths, and /CAS latency options.
File format: PDF
Size: -
MD5 Checksum: 09B2AD5D84E476D865CF52A3455ADC2D
Publication date: 07 May, 2012
Downloads: -
PDF Link: ELPIDA 2G bits DDR2 SDRAM EDE2104ABSE (512M words × 4 bits) EDE2108ABSE (256M words × 8 bits) PDF