This document is a preliminary data sheet for the 2G bits DDR2 SDRAM product. The product features a double-data-rate architecture, allowing for two data transfers per clock cycle. The high-speed data transfer is achieved through a 4-bit prefetch pipelined architecture. Bi-directional differential data strobe (DQS and /DQS) is used to transmit/receive data and capture data at the receiver. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The product is available in two organizations: 64M words × 4 bits × 8 banks or 32M words × 8 bits × 8 banks. It supports multiple data rates, page sizes, burst lengths, and /CAS latency options.
The Elpida EDE2104ABSE and EDE2108ABSE are 2‑Gbit DDR2 SDRAM parts offered in 68‑ball FBGA packages. The EDE2104ABSE provides a 512M‑word ×4‑bit organization, while the EDE2108ABSE offers a 256M‑word ×8‑bit organization. Both devices operate with a 1.8 V SSTL‑18 interface and support data rates up to 800 Mbps.
The datasheet details electrical specifications, pin configurations, timing parameters, and recommended operating conditions. It also includes ordering information, package drawings, and handling precautions for reliable integration into electronic equipment.
| Density | 2 G bits |
|---|---|
| Organization | 64M words × 4 bits × 8 banks (EDE2104ABSE); 32M words × 8 bits × 8 banks (EDE2108ABSE) |
| Package | 68‑ball FBGA |
| Power supply | VDD, VDDQ = 1.8 V ±0.1 V |
| Interface | SSTL_18 |
| Data rate | 800 Mbps / 667 Mbps / 533 Mbps (max) |
| Burst lengths | 4, 8 |
| CAS latency | 3‑6 |
| Operating temperature | 0 °C to +95 °C |
| Storage temperature | -55 °C to +100 °C |
| Power dissipation | 1.0 W |
Both parts are supplied in a 68‑ball FBGA package.
The devices are rated for an operating case temperature from 0 °C up to +95 °C.
They require a 1.8 V supply (VDD, VDDQ) with a tolerance of ±0.1 V.
The parts support maximum data rates of 800 Mbps, 667 Mbps, or 533 Mbps.