Cirrus Logic CS5510/11/12/13 Datasheet

The CS5510/11/12/13 are low-cost, easy-to-use, ∆Σ analog-to-digital converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are available in a space-efficient, 8-pin SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. To accommodate these applications, the ADCs include a fourth-order ∆Σ modulator and a digital filter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than 80 dB of simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an external clock source. Low-power, flexible supply configurations, compact pinout.


Cirrus Logic CS5510/11/12/13 Datasheet - cover page
Brand
Cirrus Logic
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
24
File format
PDF
File size
404 KB
Published
12 April, 2012
Updated
29 September, 2023
MD5 checksum
6AD01133DD292688322B4697471B2E15

About this manual

The CS5510/11/12/13 family are low‑cost, 8‑pin delta‑sigma analog‑to‑digital converters offering 16‑bit (CS5510/11) and 20‑bit (CS5512/13) performance. They are intended for weigh‑scale, process‑control and other industrial applications, featuring a fourth‑order modulator, digital filter, and flexible supply options.

The document provides detailed analog and digital characteristics, dynamic performance, absolute maximum ratings, switching timing, ordering information, and package dimensions for each variant, along with recommended supply configurations and power‑consumption figures.

What's inside

  • Characteristics and Specifications
  • General Description
  • Analog Characteristics
  • Digital Characteristics
  • Dynamic Characteristics
  • Absolute Maximum Ratings
  • Switching Characteristics
  • Ordering Information
  • Environmental, Manufacturing, & Handling Information
  • Package Dimensions

Specifications

Linearity Error (CS5510/11)0.0015% FS
Linearity Error (CS5512/13)0.0007% FS
Noise‑free ResolutionUp to 17 Bits
Supply Voltage ConfigurationV+ = 5 V, V‑ = 0 V (dual‑supply options available)
Power Consumption (Normal Mode)2.5 mW
Power Consumption (Sleep Mode)10 µW
Output Word Rate (CS5511/13)107 Sps (up to +50%)
Analog Input Range0.250 V to 5 V
Package8‑pin SOIC

Frequently asked questions

What is the typical linearity error for the CS5510/11?

The CS5510/11 achieves a typical linearity error of 0.0015 % full‑scale.

What are the power‑consumption levels in normal and sleep modes?

In normal operation the device consumes about 2.5 mW, while in sleep mode it draws roughly 10 µW.

Which supply voltages are supported?

The ADC can be powered with a single‑supply configuration of V+ = 5 V and V‑ = 0 V, and also supports multiple dual‑supply arrangements.

What is the output word rate for the CS5511/13 variant?

The CS5511/13 provides an output word rate of 107 samples per second, with up to a 50 % increase possible.

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