Intersil 82C55A Address to Read/Write Set Up Time Technical Brief

About this manual

The brief describes the read/write logic implementation of the 51864 mask (L7 version) of the 82C55A PPI. It details how the "Address Stable Before READ" (tAR) and "Address Stable Before WRITE" (tAW) timing requirements are maintained, but a falling edge on the READ or WRITE signal now disables further changes on the address lines during the operation.

The impact note states that this disabling should not affect any application because the READ or WRITE signal is always unasserted before the address changes and re‑asserted after the new address is established. However, test equipment may flag the difference as a failure, so designers should verify timing data before ordering.

What's inside

• Introduction
• Address Setup Timing
• Impact
• Contact Information

Specifications

Frequently asked questions

What happens to the address lines when a READ or WRITE signal falls on the 51864 mask version?

A falling edge on the READ or WRITE signal disables further changes on the address lines (AO and A1) during the operation.