Analog Devices AD9866 Mixed‑Signal Front‑End Datasheet

AD9866 is a broadband modem mixed-signal front end with 12-bit D/A converter, 2×/4× interpolation filter, 200 MSPS DAC update rate, integrated 23 dBm line driver and 19.5 dB gain control, 12-bit, 80 MSPS A/D converter, -12 dB to +48 dB low noise RxPGA (< 2.5 nV/rtHz), third order programmable low-pass filter, flexible digital data path interface, half- and full-duplex operation, backward compatible with AD9975 and AD9876, various power-down/reduction modes, internal clock multiplier (PLL), 2 auxiliary programmable clock outputs, available in 64-lead chip scale package or bare die.


Analog Devices AD9866 Mixed‑Signal Front‑End Datasheet - cover page
Brand
Analog Devices
Category
Other device
Document type
Datasheet
Language
English
Pages
48
File format
PDF
File size
1.2 MB
Published
23 March, 2012
Updated
30 September, 2023
Model
AD9866
MD5 checksum
9C619CFF033EF9758C4B486F0E561D82

About this manual

The AD9866 mixed‑signal front‑end (MxFE) integrates a 12‑bit DAC, a 12‑bit ADC, programmable gain amplifiers, interpolation filters and a PLL‑based clock multiplier. It supports half‑ and full‑duplex operation for broadband modem applications such as VDSL and power‑line networking.

The device is supplied in a 64‑lead lead‑frame chip‑scale package (LFCSP) and operates from a 3.3 V supply range (‑40 °C to +85 °C). Detailed specifications cover DAC/ADC performance, power consumption, digital interface timing and pin functions.

What's inside

  • Specifications
  • Tx Path Specifications
  • Rx Path Specifications
  • Power Supply Specifications
  • Digital Specifications
  • Serial Port Timing Specifications
  • Half‑Duplex Data Interface Timing
  • Full‑Duplex Data Interface Timing
  • Absolute Maximum Ratings
  • Ordering Guide

Specifications

Resolution (DAC/ADC)12 bits
DAC Update Rate200 MSPS
Supply Voltage (AVDD)3.3 V ±5 %
Package64‑lead LFCSP (CP‑64‑3)

Frequently asked questions

What is the DAC update rate of the AD9866?

The DAC operates at a full‑scale update rate of 200 MSPS.

What supply voltage does the AD9866 require?

The analog supply (AVDD) is 3.3 V with a tolerance of ±5 %.

In which package is the AD9866 offered?

It is offered in a 64‑lead lead‑frame chip‑scale package (LFCSP, CP‑64‑3).

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