This document describes two errors of MAXQ612 revision B1 chip. The first error is that when the internal oscillator (PLL) is used in divide-by-4 mode as system clock, the watchdog timer reset will lock the IC, and a power cycle is required to recover. The second error is that flash word programming and page erase operations do not complete successfully when invoked with clock divide-by-2, divide-by-4, or divide-by-8 modes active.
The errata sheet documents several functional discrepancies observed in MAXQ612 revision B1 devices and offers recommended workarounds. It applies only to components marked with the B1 revision code on the package.
Key issues include watchdog timer reset locking the IC, flash programming failures in clock‑divided modes, inadvertent erasure of system code when memory protection is enabled, and problems with certain instructions and interrupt priorities. The document also provides a revision history for reference.
The watchdog timer reset locks the IC in reset, requiring a power cycle to recover.
Flash word programming and page erase operations do not complete successfully when the system clock is divided; the workaround is to set the clock to divide‑by‑1 before performing these operations.
Entering debug mode in upper memory causes the debug engine to drop the privilege level, generating a memory fault upon return from the debug code.