Guangzhou ZLG AN05320101 FIFO Application Note

About this manual

The document introduces the FIFO function of the Actel ProASIC3 FPGA series, describing its internal hardware FIFO controller, available status signals (FULL, EMPTY, AFULL, AEMPTY), and the configurable data‑width/depth options. It also provides timing waveforms and a simple usage example.

Detailed sections cover the FIFO characteristics, internal signal definitions, configuration of data width and depth via WW and RW signals, example implementations for both hardware‑controlled and software‑controlled FIFOs, and important precautions and reference material. This manual is written in Chinese.

What's inside

• Overview
• FIFO Features
• FIFO Internal Architecture
• FIFO Usage Examples
• Precautions
• References
• Disclaimer

Specifications

Frequently asked questions

What signals indicate FIFO status?

The FIFO provides FULL, EMPTY, AFULL, and AEMPTY signals to indicate whether it is full, empty, almost full, or almost empty.

How are data width and depth configured?

Data width and depth are set using the WW and RW control signals as described in Table 1 of the document.