This document is the Cortex-M3 Technical Reference Manual from Guangzhou ZLG MCU Development Co., Ltd. It provides an overview of the processor, programming model, system control, memory mapping, exceptions, clock, and reset.
This manual describes the Cortex-M3 core architecture used in ZLG microcontrollers, covering the programmer's model, system control registers, and memory organization. It includes sections on interrupt handling, power management, and debugging interfaces.
Additional chapters detail the Memory‑Mapping and Bit‑Banding features, MPU configuration, and JTAG‑DP / SW‑DP debug ports, with appendices containing company contact information and revision history. This manual is written in Japanese.
| Processor core | Cortex-M3 |
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