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The CD74AC245 and CD74ACT245 are octal-bus transceivers that utilize the Harris Advanced CMOS Logic technology. They are non-inverting three-state bidirectional transceiver- buffers intended for two-way transmission from “A” bus to “B” bus or “B” bus to “A”. The logic level present on the direction input (DIR) determines the data direction. When the output enable input (OE) is HIGH, the outputs are in the high- impedance state.
The CD74AC238 decoder/demultiplexer is designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times.
CD74AC175 and CD74ACT175 are quad D flip-flops with reset that utilize the Harris Advanced CMOS Logic tech- nology. Information at the D input is transferred to the Q and Q outputs on the positive-going edge of the clock pulse. All four flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a LOW logic level independent of the clock.
This document describes the features and characteristics of Harris Semiconductor's CD74AC174 and CD74ACT174 products, including buffered inputs, propagation delay, ESD protection, CMOS process and circuit design, low power consumption, balanced propagation delays, operation range of 1.5V to 5.5V, noise immunity, and output drive current.
The CD54AC163 and CD74AC163 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of
The CD54AC161 and CD74AC161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function is
This document describes the features and characteristics of Harris Semiconductor's CD74AC153 and CD74ACT153 dual 4-input multiplexers, including buffered inputs, propagation delay, ESD protection, CMOS process and circuit design, power consumption, balanced propagation delays, noise immunity, and output drive current.
