MOTOROLA Manuals

MT870 is a touch screen mobile phone launched by Motorola, which supports 3G TD-SCDMA network, providing fast and convenient internet experience and an 8-megapixel camera. The phone has a sleek design, a large screen, a cool operating interface, and offers a new user experience.

Motorola Media Link Quick Start Guide, introduces the use of software, system requirements, supported formats, installation methods, setup methods, contact information and other content.

The document describes the features and characteristics of the 2N4856A supplier.

This complete new line of zener/tvs diodes offers a 2.5 watt series in a micro miniature, space saving surface mount package. The Powermite zener/tvs diodes are designed for use as a tvs or a regulation device in automotive and telecommunication applications where efficiency, low leakage, size/height and profile are important.

This document is about the product specification of Motorola, introducing the features and characteristics of 68HC05J5A.

The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP) that combines an efficient 16-bit digital signal processing core, program and data memories, multiple peripherals, and system support circuitry on a single semiconductor chip. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL), making it a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations.

This integrated circuit is intended for GSM class IV handsets. The device is specified for 2.5 Watts output power and 43% minimum power added efficiency under GSM signal conditions at 3.6 Volt supply voltage. To achieve this superior performance, Motorola's planar GaAs MESFET process is employed. The device is packaged in the PFP-16 Power Flat Pack package which gives excellent thermal performance through a solderable backside contact.

The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0-PD3 map into the Triton II chip set for auto-configuration of the cache control. Pentium-Style Burst Counter on Chip. Pipelined Data Out. 160 Pin Card Edge Module. Address Pipeline Supported by ADSP Disabled with Ex. All Cache Data and Tag I/Os are TTL Compatible. Three State Outputs. Byte Write Capability. Fast Module Clock Rate: 66 MHz. Fast SRAM Access Times: 15 ns for Tag RAM, 8 ns for Data RAMs. One-Cycle Deselect Data RAMs. Decoupling Capacitors for Each Fast Static RAM. High Quality Multi-Layer FR4 PWB with Separate Power and Ground.

The MC74LVQ138 is a high performance, 1–of–8 decoder/ demultiplexer operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. The MC74LVQ138 is suitable for memory address decoding and other TTL level bus oriented applications.

MC54/74HC138A is the upgraded version of MC54/74HC138, which supports LSTTL output. This chip can decode three-bit address into eight outputs, and supports three selection functions: decoding, cascading and selection.

The MC10103 is a quad 2-input OR gate that provides one gate with OR/NOR outputs. It has low power consumption and fast response time.