MOTOROLA Manuals

The MC10E/100E104 is a quint 2-input AND/NAND gate from Motorola that has a maximum propagation delay of 600ps and can output OR and NOR logic levels.

The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. If only the F outputs are to be used, the Q outputs need not be terminated.

The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH.

The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH.

This is a summary of the MC10E/100E112 datasheet. It is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. The device can be used as an ECL memory address fan-out driver, or as a clock driver, although the MC10E/100E111 is specifically designed for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the E212 device.

MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. An internally generated reference supply (VBB) is available for single-ended reception. It has a maximum propagation delay of 500ps, VBB supply output, dedicated VCCO pin for each receiver, extended 100E VEE range of -4.2V to -5.46V, and 75kΩ input pulldown resistors.

This datasheet provides the data of MC10E/100E122, including pinout, electrical characteristics, package etc.

MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs, released by Motorola in 1996. The device can be clocked separately by keeping the common clock (CC) low and using the clock enable (CE) inputs for clocking. Common clocking is achieved by keeping the CE inputs low and using CC to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.

MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading of multiple E136’s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter.

MC10E/100E141 is an 8-bit full-function shift register. It performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0-D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 – D8 accepting parallel input data.

MC10E/100E150 is a 6-bit D latch with differential outputs produced by Motorola. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.

The MC10E/100E150 is a 6-bit D latch with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.