The document describes the features and characteristics of the ispGAL22V10 product, including programmable interface, high performance technology, logic macrocells, etc. The product is suitable for applications such as DMA control, state machine control, high-speed graphics processing, and software-driven hardware configuration.
ispGAL®22LV10 is a PLD device from Lattice Semiconductor Corp. that features high performance and low power consumption. It is manufactured using E2CMOS® technology and has a maximum propagation delay of 4 ns and a 3.3V low voltage interface standard. The device also has more than 10,000 program/erase cycles and is compatible with standard 22LV10/22V10 devices.
The ispClock 5600 family is an in-system programmable, zero-delay clock generator with a universal fan-out buffer. It operates in the range of 10MHz to 320MHz and offers low output to output skew (<50ps) and low jitter peak-to-peak (<60ps). It has up to 20 programmable fan-out buffers with various programmable features such as output standards, output impedance, slew rate, and individual enable controls. The family also includes a fully integrated high-performance PLL with programmable lock detect and multiply/divide ratio control. It supports precision programmable phase adjustment per output, up to five clock frequency domains, and flexible clock reference and external feedback inputs.
ispLSI 2032E is a high-density, fast, easy-to-use, in-system programmable PLD with 1000 PLD gates, 32 I/O pins, two dedicated inputs, 32 registers, high-speed global interconnect, wide input gating for fast counters, state machines, address decoders, etc.
This document describes the features and characteristics of the ispLSI ® 1048E high-density programmable logic chip, including high-density programmable logic, high-performance E2CMOS® technology, and in-system programmability.
The document describes the features and characteristics of a high-density programmable logic product, including the number of PLD Gates, I/O Pins, Registers, maximum operating frequency, and input/output compatibility.
ispLSI® 1024EA is a high density programmable logic device from Infineon with 4000 PLD gates and 48 I/O pins, supports IEEE 1149.1 boundary scan testing, and can be programmed in-system.
ispLSI ® 1024/883 is a high-density PLD with 4000 PLD gates, 48 I/O pins, six dedicated inputs, 144 registers, and can be used for fast counters, state machines, address decoders, etc.
The MACH 5 CPLD Family Fifth Generation MACH Architecture is a high-density, high-performance, and high-integration CPLD device from Microchip Technology Inc. It has high logic density, high I/O, high performance, flexible logic design architecture, advanced system integration capabilities, and high performance, high cost-effective characteristics, suitable for a wide range of applications.
This document describes the features and characteristics of the MACH 4 CPLD family, which includes high-performance E2CMOS® programmable logic with flexible architecture, high speed, and programmability.
GAL20V8 is a high performance E2CMOS PLD (programmable logic device) launched by Lattice company in August 2006. It has a maximum propagation delay of 5ns, Fmax=166MHz, 4ns maximum from clock input to data output, UltraMOS® Advanced CMOS technology, 50% to 75% lower power consumption, 8 output logic macrocells, preload and power-on reset.
LA-ispPAC-POWR1014/A is a programmable power supply supervisor, reset generator and sequencing controller from the automotive family of Lattice Semiconductor Corp. Features include simultaneous monitoring of up to 10 power supplies, provision of up to 14 output control signals, programmable digital and analog circuitry, AEC-Q100 tested and qualified, embedded PLD for sequence control, embedded programmable timers, analog input monitoring, high-voltage FET drivers, and 2-wire (I2C/SMBus™ compatible) interface.
GAL20V8 is a high-performance E2CMOS PLD (programmable logic device) from Lattice Semiconductor Corp. It has a maximum propagation delay of 5 ns and a maximum operating frequency of 166 MHz. The device uses UltraMOS advanced CMOS technology, with power consumption 50% to 75% lower than that of bipolar devices. Typical current for low-power devices is 75mA, and typical current for quarter-power devices is 45mA. In addition, the device has active pull-ups on all pins, reconfigurable logic, reprogrammable cells, 100% tested / 100% yields, high-speed electrical erasure (<100ms), and 20-year data retention.
The Lattice ispXPGA Family of radio solutions is a series of SRAM-based FPGAs that offer ultra-fast boot time, easy configuration, and high performance. The family features up to 1.25M system gates and up to 496 I/O, making it ideal for high-performance, reconfigurable wireless and communications applications.
The MACH 5 CPLD Family Fifth Generation MACH Architecture is a logic integrated circuit product with high logic density and input/output interfaces to support various application needs. It also features high-performance characteristics, flexible architecture design for convenient logic design and system integration. It supports advanced capabilities such as boundary scan testing and programmable security bit. It is based on advanced E2CMOS process, providing high-performance and cost-effective solutions.
