Intersil manuals, page 45
intersil HSP50214B Manual
The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. It performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.
intersil HSP50016 Manual
The HSP50016 is a high performance digital down converter that performs down conversion, filtering and decimation on sampled data streams of up to 16 bits in width and up to a 75 MSPS data rate.
intersil HSP43220 Manual
The HSP43220 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220 offers a single chip solution to signal processing applications which have historically required several boards of ICs. This reduction in component count results in faster development times as well as reduction of hardware costs. The HSP43220 is implemented as a two stage filter structure. As seen in the block diagram, the first stage is a high order decimation filter (HDF) which utilizes an efficient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a finite impulse response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384. The HSP43220 accepts 16-bit parallel data in 2’s complement format at sampling rates up to 33MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220 has low power consumption and operates over a wide supply voltage range of 1.8V to 3.3V and does not require an external clock.
intersil HSP43216 Manual
The HSP43216 Halfband Filter is a halfband filter manufactured by ADI. It can process 16-bit data with a maximum data rate of 52MSPS. When used with an external multiplexer or demultiplexer, the processing throughput of the part can be easily doubled to 104MSPS.
intersil HSP43168Manual
This document is the official datasheet for HSP43168 Dual FIR Filter. HSP43168 Dual FIR Filter is a low power fully static design with 8 sample input channels and two independent 8-bit FIR filters. It supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients.
intersil HSP43124 Manual
The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided. For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an on-board ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter. The serial interface for 3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface.
intersil HSP50210 Manual
This document introduces the Intersil HSP50210 Digital Costas Loop, which can be used to demodulate BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM waveforms.
intersil HSP50110 Manual
This is the technical manual of HSP50110 Digital Quadrature Tuner. The tuner provides many of the functions required for digital demodulation, including carrier LO generation and mixing, baseband sampling, programmable bandwidth filtering, baseband AGC, and IF AGC error detection. Serial control inputs are provided which can be used to interface with external symbol and carrier tracking loops. These elements make the DQT ideal for demodulator applications with multiple operational modes or data rates. The DQT may be used with HSP50210 Digital Costas Loop to function as a demodulator for BPSK, QPSK, 8-PSK OQPSK, FSK, FM, and AM signals. The DQT processes a real or complex input digitized at rates up to 52 MSPS. The channel of interest is shifted to DC by a complex multiplication with the internal LO. The quadrature LO is generated by a numerically controlled oscillator (NCO) with a tuning resolution of 0.012Hz at a 52MHz sample rate. The output of the complex multiplier is gain corrected and fed into identical low pass FIR filters. Each filter is comprised of a decimating low pass filter followed by an optional compensation filter. The decimating low pass filter is a 3 stage Cascaded-Integrator-Comb (CIC) filter. The CIC filter can be configured as an integrate and dump filter or a third order CIC filter with a (sin(X)/X)3 response. Compensation filters are provided to flatten the (sin(X)/X)N response of the CIC. If none of the filtering options are desired, then the input is directly fed into the FIR filter.
intersil X28HC64 Manual
The X28HC64 is an 8K x 8 EEPROM fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable non-volatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs. The X28HC64 supports a 64-byte page write operation, with an average write cycle of 2ms, and a complete memory rewrite time of 0.25 seconds. The chip has a durability of 1 million cycles and a data retention of 100 years.
intersil X28HC256 Manual
The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM that is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.
intersil X28C512 X28C513 Manual
Intersil's X28C512, X28C513 are 64K x 8 EEPROMs fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. They feature the JEDEC approved pin out for byte wide memories, compatible with industry standard EPROMS. The X28C512, X28C513 support a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512, X28C513 also feature DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512, X28C513 support the software data protection option.
intersil X28C010 X28HT010 Manual
This datasheet provides detailed information on Intersil X28C010/X28HT010 5V, Byte Alterable EEPROM
intersil ICL232 Manual
The ICL232 is a dual RS-232 transmitter/receiver interface circuit that meets all ElA RS-232C and V.28 specifications. It requires a single +5V power supply, and features two onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. The drivers feature true TTL/CMOS input compatibility, slew- rate-limited output, and 300Ω power-off source impedance. The receivers can handle up to +30V, and have a 3kΩ to 7kΩ input impedance. The receivers also have hysteresis to improve noise rejection.
intersil ICL3238E Manual
intersil ICL3237E Manual
The ICL3237E is a family of 3.0V to 5.5V powered RS-232 transmitters/receivers that meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, it provides ±15kV ESD protection (IEC61000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins).