NXP 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch datasheet

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.


NXP 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch datasheet - cover page
Brand
NXP
Category
transparent latch
Document type
Datasheet
Language
English
Pages
18
File format
PDF
File size
238 KB
Published
15 May, 2014
Updated
25 September, 2023
Model
74LVC
MD5 checksum
985D2F8F0821373E7EEEC91718D370AC

About this manual

The NXP 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches designed for bus-oriented applications. They feature separate D-type inputs with optional bus hold (74LVCH16373A only) and 3-state outputs. The devices support mixed 3.3 V and 5 V applications, with inputs drivable from either voltage level and outputs capable of withstanding up to 5.5 V when disabled.

What's inside

  • General description
  • Features and benefits
  • Ordering information
  • Functional diagram
  • Pinning information
  • Functional description
  • Limiting values
  • Recommended operating conditions
  • Static characteristics

Specifications

Supply voltage range1.2 V to 3.6 V
Input voltage tolerance5 V tolerant
Output voltage tolerance (disabled)5.5 V
Operating temperature range-40 °C to +125 °C

Frequently asked questions

What is the difference between the 74LVC16373A and 74LVCH16373A?

The 74LVCH16373A includes separate D-type inputs with bus hold for each latch, which the 74LVC16373A does not have.

Can these latches be used in mixed 3.3 V and 5 V applications?

Yes, inputs can be driven from either 3.3 V or 5 V devices, and outputs can withstand up to 5.5 V when disabled.

What is the function of the OE input?

When OE is LOW, the latch contents are available at the outputs; when OE is HIGH, the outputs go to the high impedance OFF-state.

Download PDF (238 KB)

More NXP Manuals


View all NXP manuals →