The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to dr
The NXP 74HC4017 and 74HCT4017 are 5-stage Johnson decade counters featuring 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1), and an overriding asynchronous master reset input (MR). The counter advances based on specific clock transitions at CP0 or CP1 and can be cascaded using the Q5-9 output.
| Supply voltage range (74HC4017) | 2.0 V to 6.0 V |
|---|---|
| Supply voltage range (74HCT4017) | 4.5 V to 5.5 V |
| Operating temperature range | -40 °C to +125 °C |
| Number of decoded outputs | 10 (Q0 to Q9) |
| Clock inputs | Two (CP0 and CP1) |
| Reset input type | Asynchronous master reset (MR) |
A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs.
The Q5-9 output, which is LOW while the counter is in states 5 through 9, can be used to drive the CP0 input of the next counter.
Yes, following any illegal code the counter returns to a proper counting mode within 11 clock pulses.