Specification defining address space, interrupt mapping, firmware‑kernel parameter passing and SMBIOS rules for Loongson CPU development systems.
This document specifies the address‑space layout, interrupt configuration, firmware‑to‑kernel parameter passing mechanisms, and SMBIOS implementation conventions for Loongson 2‑ and 3‑series CPU development systems. It includes both a general part and detailed appendices for specific board configurations.
The specification is intended for hardware designers and firmware developers who need to ensure compatibility between firmware, bootloaders, and operating system kernels across different Loongson platforms. This manual is written in Chinese.
| Low‑end memory space size | 256 MB (0x0000_0000 – 0x0FFF_FFFF) |
|---|---|
| High‑end memory base address (default) | 0x9000_0000 |
| DMA address mapping for 7A bridge | 1:1 mapping (DMA address equals physical address) |
| Interrupt numbers reserved for PCIe devices on 7A bridge | 0‑55 |
The default high‑end memory base address is 0x9000_0000.
For the 7A bridge, DMA addresses are mapped 1:1 to physical memory addresses.
Interrupt numbers 0 through 55 are reserved for PCIe devices on the 7A bridge.
The low‑end memory range is 0x0000_0000 to 0x0FFF_FFFF, covering 256 MB.