This guide covers advanced Sigma-Delta ADC concepts including idle tones, multi-bit architectures, MASH, and bandpass converters with example applications.
This guide, authored by Walt Kester, introduces advanced concepts for Sigma-Delta (Σ-Δ) ADCs beyond basic principles. It discusses the issue of idle tones in first-order modulators and explains how higher-order loops or multi-bit architectures can mitigate these effects. The document also covers Multi-stage Noise Shaping (MASH) as a stable alternative to high-order single-loop designs. This manual is written in Chinese.
| Power Supply Range | 2.7 V to 5.25 V |
|---|---|
| Typical Power Consumption | 380 μA |
| Throughput Rate Range | 4.17 Hz to 500 Hz |
| Gain Settings | 1, 2, 4, 8, 16, 32, 64, 128 |
| Dynamic Range (A-weighted) | 105 dB |
Higher-order loops are difficult because the comparator is a non-linear element, and its effective gain is inversely proportional to the input level, which can cause instability.
MASH converters ensure circuit stability by cascading stable first-order loops, avoiding the instability issues associated with high-order single loops.