TOSHIBA TC4015BP/TC4015BF Manual


TOSHIBA TC4015BP/TC4015BF Manual - cover page
Brand
Toshiba
Category
INTEGRATED CIRCUITS
Document type
Datasheet
Language
English
Pages
10
File format
PDF
File size
427 KB
Published
23 September, 2011
Updated
18 October, 2026
Model
15BP
MD5 checksum
2B41B64C5E49F809B51B2B4709CFF8C5

About this manual

The TC4015BP/BF/BFN is a Toshiba CMOS digital integrated circuit containing two independent 4-stage shift registers with serial input and parallel output. All D-type flip-flops in each stage share a common RESET input, allowing asynchronous clearing by an external signal at arbitrary timing. Each flip-flop is triggered by the rising edge of the CLOCK input.

The device is available in DIP16, SOP16, and SOL16 packages, with typical weights of 1.00 g, 0.18 g, and 0.13 g respectively. Recommended DC supply voltage ranges from 3 to 18 V, and the operating temperature range is −40 to 85 °C.

What's inside

  • Pin Assignment
  • Truth Table
  • Logic Diagram
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • Static Electrical Characteristics
  • Dynamic Electrical Characteristics
  • Waveforms for Measurement of Dynamic Characteristics
  • Package Dimensions
  • Restrictions on Product Use

Specifications

DC supply voltage3 to 18 V
Operating temperature range−40 to 85 °C
Storage temperature range−65 to 150 °C
DC input current±10 mA
Power dissipation300 mW (DIP) / 180 mW (SOIC)

Frequently asked questions

What kind of device is the TC4015B?

It is a CMOS dual 4-stage static shift register with serial input and parallel output.

How does the asynchronous clear operation work?

It is achieved by an external RESET signal at arbitrary timing, resetting all stages to “L”.

What triggers the flip-flop in each stage?

The rising edge of the CLOCK input triggers each flip-flop stage.

Is the JEDEC SOP package available in Japan?

No, the xxxFN (JEDEC SOP) package is not available in Japan.

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