The document describes an advanced high-speed CMOS octal D-type latch with three-state outputs and non-inverting function. The product is fabricated using sub-micron silicon gate and double-layer metal wiring C2MOS technology, and it features high noise immunity, low power dissipation, and low noise. It has power down protection on inputs and is compatible with 5V to 3V interfaces. All inputs and outputs are equipped with protection circuits against static discharge, providing 2KV ESD immunity and transient excess voltage protection.
This document is a datasheet for the 74VHC573, an advanced high-speed CMOS octal D-type latch with 3-state non-inverting outputs. Fabricated with sub-micron silicon gate and double-layer metal wiring CMOS technology, the device features high noise immunity and power-down protection on inputs.
The datasheet provides comprehensive technical specifications including absolute maximum ratings, recommended operating conditions, and DC and AC electrical characteristics. It details the pin configuration, truth table, and logic diagrams, along with order codes for SOP and TSSOP packages.
| Propagation Delay (Typical) | 5.0 ns |
|---|---|
| Low Power Dissipation (Max) | 4 mW |
| Operating Voltage Range | 2V to 5.5V |
| ESD Immunity | 2KV |
| Operating Temperature Range | -55 to 125 °C |
| Package Types | SOP, TSSOP |
The device operates with a supply voltage range of 2V to 5.5V.
Yes, the device can be used to interface 5V to 3V logic levels.
The maximum low power dissipation is 4 mW at 25°C.