This document describes the features and characteristics of the M95M02-DR product, including compatibility with the Serial Peripheral Interface (SPI) bus, 2 Mb EEPROM memory array, 256-byte page size, additional write lockable page, write protect options, clock frequency, single supply voltage range, write cycle durability, data retention period, and enhanced ESD protection.
The STMicroelectronics M95M02-DR is a 2-Mbit electrically erasable programmable memory (EEPROM) accessed by an SPI bus. Its memory array is 256 Kbytes, or 1024 pages of 256 bytes each, and it operates from a single supply voltage of 1.8 V to 5.5 V. The device also offers an additional 256-byte Identification Page that can be written and later permanently locked in Read-only mode.
This datasheet covers the M95M02-DR signal descriptions, SPI bus connection, operating features, memory organization, instruction set, and ECC and write cycling. It also provides DC and AC parameters, package mechanical data for SO8N and WLCSP packages, and part numbering information.
| Memory array | 2 Mb (256 Kbytes) |
|---|---|
| Page size | 256 bytes |
| Clock frequency | 5 MHz |
| Supply voltage | 1.8 V to 5.5 V |
| Write cycles | More than 1 million |
| Data retention | More than 40 years |
| Write time | Byte Write within 10 ms; Page Write within 10 ms |
| Packages | SO8N (150 mils width) and WLCSP |
| Operating temperature range | –40 to 85 °C |
It has a 2-Mbit memory array, equivalent to 256 Kbytes or 1024 pages of 256 bytes each.
It operates from a single supply voltage of 1.8 V to 5.5 V.
The additional 256-byte page can store unique identification parameters or production-line parameters and can later be permanently locked in Read-only mode.
It is available in the SO8N package with 150 mils width and in the WLCSP package.