This document describes the features and characteristics of the STM7007 single-chip hardware accelerated encryption engine, including world-class encryption engine, support for symmetric and asymmetric algorithms, PCI Express interface, etc.
The STM7007 is a single-chip hardware accelerated encryption engine designed for computer and peripherals applications. It is built on STMicroelectronics' HardCache™ cryptographic channel controller and features a 65 nm process technology. The device supports symmetric algorithms including AES (Rijndael) with key lengths of 128/192/256 bits and Triple DES, as well as asymmetric algorithms like ECDSA and RSA.
The document provides detailed technical specifications, including device pinout, electrical characteristics, and PCB layout guidelines. It highlights the engine's ability to offload intensive cryptographic calculations from the system CPU and its compliance with FIPS 140-2 security level 3 and NIST certificates.
| Security Level | FIPS 140-2 security level 3 |
|---|---|
| Process Technology | 65 nm |
| Interface | PCI Express x1 |
| AES Key Lengths | 128/192/256 bits |
| Triple DES Key Lengths | 112/168 bits |
| Package Type | 32-Lead LGA 5x5 |
| Operating System Support | Windows XP, 2000, Vista, 7 |
The STM7007 supports FIPS 140-2 security level 3.
It uses a 32-Lead, 5 x 5 x 0.82 mm land grid array (LGA) package.