This is an application note about the STM8L A/D converter, which introduces the internal structure, working principle, and precision improvement methods of the converter.
The document explains the internal design principles of the switched-capacitor ADC found in the STM8L family, detailing its operation from a programmer's perspective. It covers resolution settings, clock speeds, sampling times, and various input channels including fast and slow modes.
Furthermore, it lists main types of errors such as linearity, offset, gain, and hardware design issues, offering specific techniques to minimize them. The note includes both hardware methods like analog zooming and software methods like averaging samples and digital filtering, along with source code examples for implementation.
| ADC Resolution | 6-bit, 8-bit, 10-bit or 12-bit |
|---|---|
| Maximum ADC Clock | 16 MHz |
| Minimum ADC Clock | 320 kHz |
It is 1 us when using a 16 MHz ADC clock.
The document suggests hardware methods like analog zooming and software methods such as averaging samples, digital filtering, and FFT.