AN1014 is an application note that describes the low power modes of ST7, and how to reduce power consumption by adjusting the supply voltage and clock frequency
The document details various factors affecting CMOS digital logic device power consumption, such as supply voltage, clock frequency, and active peripherals. It provides a formula for calculating predicted power use based on load capacitance, voltage, and frequency.
It describes six main power management modes available in ST7 devices: Standard Run Mode, Slow Mode, Wait Mode, Slow-Wait Mode, Active-Halt Mode, and Halt Mode. The text explains the specific behavior of each mode regarding CPU, peripheral, and oscillator status to help designers choose the appropriate low-power state for their application.
The basic explanation of this note is based on ST72F324.
Halt Mode is the lowest power consumption mode without availability of Real Time Clock.
Active-Halt Mode is the lowest power consumption mode with Real Time Clock available.