This document describes how to prevent EEPROM data corruption in ST6 devices, including software and hardware solutions
The document addresses potential data corruption issues that occur when the reset signal is not properly controlled during power-up or power-down sequences, particularly with slow ramp times. It explains how the device may enter a state where functionality is not guaranteed, leading to unintended writes into the EEPROM.
Two complementary solutions are provided: a software solution involving the disabling of the enable bit in the EEPROM control register before switching off the application, and a hardware solution using a level detection circuit to force the reset input low before reaching critical voltage levels.
Data integrity can be ensured as long as the application designer follows the guidelines provided, but corruption occurs whenever the reset signal is not controlled when the power supply goes up or down.
The enable bit is automatically reset upon power on, so most cases of data corruption occur at power down because the enable bit may have been modified by user software.
The hardware solution should be used whenever the power supply rise/fall time is greater than 100ms or if the supply comes from the mains through a single resistor and diode network.